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| ds05-20908-2e fujitsu semiconductor data sheet flash memory cmos 32 m ( 4 m 8 / 2 m 16 ) bit dual operation mbm29dl34tf/bf 70 n n n n description the mbm29dl34tf/bf are a 32 m-bit, 3.0 v-only flash memory organized as 4 m bytes of 8 bits each or 2 m words of 16 bits each. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. (continued) n n n n product line up n n n n packages part no. mbm29dl34tf/bf 70 power supply voltage (v) 2.7 v to 3.6 v max address access time (ns) 70 max ce access time (ns) 70 max oe access time (ns) 30 48-pin plastic tsop (1) 48-ball plastic fbga (fpt-48p-m19) (bga-48p-m12) marking side
mbm29dl34tf/bf 70 2 ) (continued) mbm29dl34tf/bf are organized into two physical banks; bank 1 and bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. this device is the same as fujitsus standard 3 v only flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simul- taneously taking place on the other bank. in the device, a design concept called sliding bank architecture is implemented. using this concept the device can execute simultaneous operation between bank 1 and bank 2(refer to 1. simultaneous operation in n functional description.). the standard device offers access times 70 ns allowing operation of high-speed microprocessors without the wait. to eliminate bus contention the device has separate chip enable (ce ) , write enable (we ) and output enable (oe ) controls. the mbm29dl34tf/bf support pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program algorithm tm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm tm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies the proper cell margin. each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) . the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the device internally return to the read mode. the device also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore if a system reset occurs during the embedded program tm * algorithm or embedded erase tm * algorithm, the device is automatically reset to the read mode and have erroneous data stored in the address locations being programmed or erased. these locations need rewriting after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erases the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/ word at a time using the eprom programming mechanism of hot electron injection. *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. mbm29dl34tf/bf 70 3 n n n n features ? 0.17 m m m m m process technology ? simultaneous read / write operations ( dual bank ) bank 1 : 8 mbit bank 2 : 24 mbit host system can program or erase in one bank, then immediately and simultaneously read and from the other bank. zero latency between read and write operation. read - while - erase read - while - program ? single 3.0 v read , program , and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 48-pin tsop (1) (package suffix : tn - normal bend type, tr - reversed bend type) 48-ball fbga (package suffix : pbt) ? minimum 100,000 program/erase cycles ? high performance 70 ns maximum access time ? sector erase architecture eight 4 k word and sixty-three 32 k word sectors in word mode eight 8 k byte and sixty-three 64 k byte sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? hiddenrom region 256 byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp / acc input pin at v il , allows protection of outermost 2 8 bytes on boot sectors, regardless of sector protection/unprotection status. at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready / busy output ( ry / by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? low v cc write inhibit 2.5 v ? erase suspend / resume suspends the erase operation to allow a read data and/or program in another sector within the same device (continued) mbm29dl34tf/bf 70 4 (continued) ? sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin. ? in accordance with cfi (c ommon f lash memory i nterface) * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. bank and sector organization table device part number bank 1 bank 2 mbm29dl34tf bank a (sa70 to 48) bank b (sa47 to 0) mbm29dl34bf bank a (sa0 to 22) bank b (sa23 to 70) mbm29dl34tf/bf 70 5 n n n n pin assignments (continued) tsop (1) (fpt-48p-m19) a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we reset n.c. wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (marking side) normal bend mbm29dl34tf/bf 70 6 (continued) fbga (top view) marking side (bga-48p-m12) b6 b5 we b4 wp/acc b3 b2 a 7 c6 c5 a 8 c4 reset c3 c2 a 17 c1 a 2 b1 a 4 d6 a 10 d3 a 18 d2 a 6 d1 a 1 e6 e3 a 20 d4 a 19 n.c. d5 a 11 e2 a 5 e1 a 0 f6 f3 dq 2 e5 dq 7 e4 dq 5 f2 dq 0 f1 g6 g5 dq 14 dq 13 g4 dq 12 dq 4 g3 dq 10 g2 dq 8 g1 ce h6 h5 h4 v cc h3 dq 11 dq 3 h2 dq 1 h1 v ss dq 9 oe ry/by a 12 a4 a3 a2 a 3 a1 a 13 a 9 a6 a5 a 14 a 15 a 16 f4 f5 dq 6 byte dq 15 /a -1 v ss mbm29dl34tf/bf 70 7 n n n n pin description n n n n logic symbol pin function a 20 to a 0 , a -1 address input dq 15 to dq 0 data input/output ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector group unprotection byte selects byte (8-bit) or word (16-bit) mode wp /acc hardware write protection/program acceleration v cc device power supply v ss device ground n.c. no internal connection 21 a 20 to a 0 we oe ce dq 15 to dq 0 16 or 8 byte reset a -1 ry/by wp/acc mbm29dl34tf/bf 70 8 n n n n block diagram v ss v cc bank 2 address bank 1 address we ce a 20 to a 0 (a -1 ) oe byte wp/acc reset dq 15 to dq 0 ry/by state control & command register x-decoder x-decoder cell matrix (bank 2) cell matrix (bank 1) y-gating & data latch y-gating & data latch dq 15 to dq 0 status control mbm29dl34tf/bf 70 9 n n n n device bus operation mbm29dl34tf/bf user bus operations table (word mode : byte = = = = v ih ) legend : l = v il , h = v ih , x = v il or v ih , see n dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see mbm29dl34tf/bf command definitions table. *2: refer to section on 8. sector group protection in n functional description. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 2.7 v to 3.6 v *5: also used for extended sector group protection. operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 15 to dq 0 reset wp / acc standby h x xxxxxxx high-z h x autoselect manufacturer code * 1 llhlllllv id code h x autoselect device code * 1 llhhllllv id code h x extended auto-select device code * 1 l lhlhhhlv id code h x l lhhhhhlv id code h x read * 3 llha 0 a 1 a 2 a 3 a 6 a 9 d out hx output disable lhhxxxxxx high-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 d in hx enable sector group protection * 2, * 4 lv id llhlllv id xhx verify sector group protection * 2, * 4 llhlhlllv id code h x temporary sector group unprotection * 5 xxxxxxxxx x v id x reset (hardware) xxxxxxxxx high-z l x boot block sector write protection xxxxxxxxx x x l mbm29dl34tf/bf 70 10 mbm29dl34tf/bf user bus operations table (byte mode : byte = = = = v il ) legend : l = v il , h = v ih , x = v il or v ih , see n dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see mbm29dl34tf/bf command definitions table. *2: refer to section on 8. sector group protection in n functional description. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 2.7 v to 3.6 v *5: also used for extended sector group protection. operation ce oe we dq 15 /a -1 a 0 a 1 a 2 a 3 a 6 a 9 dq 7 to dq 0 reset wp / acc standby h x x x xxxxxx high-z h x autoselect manufacturer code * 1 llh l lllllv id code h x autoselect device code * 1 llh l hllllv id code h x extended auto-select device code * 1 l lh l lhhhlv id code h x l lh l hhhhlv id code h x read * 3 llha -1 a 0 a 1 a 2 a 3 a 6 a 9 d out hx output disable lhh x xxxxxx high-z h x write (program/erase) l h l a -1 a 0 a 1 a 2 a 3 a 6 a 9 d in hx enable sector group protection * 2 , * 4 lv id lllhlllv id xhx verify sector group protection * 2 , * 4 llh l lhlllv id code h x temporary sector group unprotection * 5 xxx x xxxxxx x v id x reset (hardware) xxx x xxxxxx high-z l x boot block sector write protection xxx x xxxxxx x x l mbm29dl34tf/bf 70 11 mbm29dl34tf/bf command definitions table * 1 (continued) command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data reset * 2 word 1 xxxh f0h ? ? ? ??????? byte reset * 2 word 3 555h aah 2aah 55h 555h f0h ra rd ???? byte aaah 555h aaah autoselect (device id) word 4 555h aah 2aah 55h (ba) 555h 90h 00h 04h ???? byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah program suspend 1 ba b0h ? ? ? ??????? program resume 1 ba 30h ? ? ? ??????? chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend * 3 1bab0h ? ? ? ??????? erase resume * 3 1 ba 30h ? ? ? ??????? set to fast mode word 3 555h aah 2aah 55h 555h 20h ?????? byte aaah 555h aaah fast program * 4 word 2 xxxh a0h pa pd ? ??????? byte xxxh reset from fast mode * 5 word 2 ba 90h xxxh 00h* 11 ? ??????? byte ba xxxh extended sector group protection * 6, * 7 word 4 xxxh 60h sga 60h sga 40h sga sd ???? byte query * 8 word 1 (ba) 55h 98h ? ? ? ??????? byte (ba) aah hiddenrom entry * 9 word 3 555h aah 2aah 55h 555h 88h ?????? byte aaah 555h aaah mbm29dl34tf/bf 70 12 (continued) *1 : the command combinations not described in mbm29dl34tf/bf command definitions table are illegal. *2 : both of these reset commands are equivalent. *3 : erase suspend and erase resume command are valid only during a sector erase operation. *4 : this command is valid during fast mode. *5 : the reset from fast mode command is required to return to the read mode when the device is in fast mode. *6 : this command is valid while reset = v id (except during hiddenrom mode). *7 : sector group address (sga) with (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) . *8 : the valid address are a 6 to a 0 . *9 : the hiddenrom entry command is required prior to the hiddenrom programming. *10 : this command is valid during hiddenrom mode. *11 : the date f0h is also acceptable. notes: address bits a 20 to a 11 = x = h or l for all address commands except or program address (pa) , sector address (sa) , bank address (ba) . bus operations are defined in mbm29dl34tf/bf user bus operations tables (byte = v ih and byte = v il ) ( n device bus operation). ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 20 to a 18 ) rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. sga = sector group address. the combination of a 20 to a 12 will uniquely select any sector group. sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hiddenrom area 29dl34tf (top boot type) word mode : 1ff000h to 1ff07fh byte mode : 3fe000h to 3fe0ffh 29dl34bf (bottom boot type) word mode : 000000h to 00007fh byte mode : 000000h to 0000ffh hrba = bank address of the hiddenrom area 29dl34tf (top boot type) : a 20 = a 19 = a 18 = 1 29dl34bf (bottom boot type) : a 20 = a 19 = a 18 = 0 the system should generate the following address patterns : word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a 0 , and a -1 both reset commands are functionally equivalent, resetting the device to the read mode. command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data hiddenrom program * 10 word 4 555h aah 2aah 55h 555h a0h (hra) pa pd ???? byte aaah 555h aaah hiddenrom exit * 10 word 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h ???? byte aaah 555h (hrba) aaah mbm29dl34tf/bf 70 13 mbm29dl34tf sector group protection verify autoselect codes table *1 : a -1 is for byte mode. at byte mode, dq 8 to dq 14 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. mbm29dl34tf extended autoselect code table hz: high-z * : at byte mode, dq 8 to dq 14 are high-z and dq 15 is a -1 , the lowest address. type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 a -1 * 1 code (hex) manufactures code ba* 3 v il v il v il v il v il v il 04h device code byte ba* 3 v il v il v il v il v ih v il 50h word x 2250h sector group protection sector group addresses v il v il v il v ih v il v il 01h* 2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h a -1 /0 000000000000100 device code byte* 50eh a -1 hzhzhzhzhzhzhz01010000 word 2250eh 0 0 10001001010000 sector group protection 01h a- 1 /0 000000000000001 mbm29dl34tf/bf 70 14 mbm29dl34bf sector group protection verify autoselect codes table *1 : a -1 is for byte mode. at byte mode, dq 8 to dq 14 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. mbm29dl34bf extended autoselect code table hz: high-z * : at byte mode, dq 8 to dq 14 are high-z and dq 15 is a -1 , the lowest address. type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 a -1 * 1 code (hex) manufactures code ba* 3 v il v il v il v il v il v il 04h device code byte ba* 3 v il v il v il v il v ih v il 53h word x 2253h sector group protection sector group addresses v il v il v il v ih v il v il 01h* 2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h a -1 /0 000000000000100 device code byte* 53h a -1 hzhzhzhzhzhzhz01010011 word2253h0010001001010011 sector group protection 01h a- 1 /0 000000000000001 mbm29dl34tf/bf 70 15 n n n n sector-erase architecture sector address table ( mbm29dl34tf ) bank sec- tor sector address sector size ( kbytes/ kwords) ( 8) address range ( 16) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa0 0 0 0 0 0 0 x x x x 64/32 000000h to 00ffffh 000000h to 007fffh sa1 0 0 0 0 0 1 x x x x 64/32 010000h to 01ffffh 008000h to 00ffffh sa2 0 0 0 0 1 0 x x x x 64/32 020000h to 02ffffh 010000h to 017fffh sa3 0 0 0 0 1 1 x x x x 64/32 030000h to 03ffffh 018000h to 01ffffh sa4 0 0 0 1 0 0 x x x x 64/32 040000h to 04ffffh 020000h to 027fffh sa5 0 0 0 1 0 1 x x x x 64/32 050000h to 05ffffh 028000h to 02ffffh sa6 0 0 0 1 1 0 x x x x 64/32 060000h to 06ffffh 030000h to 037fffh sa7 0 0 0 1 1 1 x x x x 64/32 070000h to 07ffffh 038000h to 03ffffh sa8 0 0 1 0 0 0 x x x x 64/32 080000h to 08ffffh 040000h to 047fffh sa9 0 0 1 0 0 1 x x x x 64/32 090000h to 09ffffh 048000h to 04ffffh sa10 0 0 1 0 1 0 x x x x 64/32 0a0000h to 0affffh 050000h to 057fffh sa11 0 0 1 0 1 1 x x x x 64/32 0b0000h to 0bffffh 058000h to 05ffffh sa12 0 0 1 1 0 0 x x x x 64/32 0c0000h to 0cffffh 060000h to 067fffh sa13 0 0 1 1 0 1 x x x x 64/32 0d0000h to 0dffffh 068000h to 06ffffh sa14 0 0 1 1 1 0 x x x x 64/32 0e0000h to 0effffh 070000h to 077fffh sa15 0 0 1 1 1 1 x x x x 64/32 0f0000h to 0fffffh 078000h to 07ffffh sa16 0 1 0 0 0 0 x x x x 64/32 100000h to 10ffffh 080000h to 087fffh sa17 0 1 0 0 0 1 x x x x 64/32 110000h to 11ffffh 088000h to 08ffffh sa18 0 1 0 0 1 0 x x x x 64/32 120000h to 12ffffh 090000h to 097fffh sa19 0 1 0 0 1 1 x x x x 64/32 130000h to 13ffffh 098000h to 09ffffh sa20 0 1 0 1 0 0 x x x x 64/32 140000h to 14ffffh 0a0000h to 0a7fffh sa21 0 1 0 1 0 1 x x x x 64/32 150000h to 15ffffh 0a8000h to 0affffh sa22 0 1 0 1 1 0 x x x x 64/32 160000h to 16ffffh 0b0000h to 0b7fffh sa23 0 1 0 1 1 1 x x x x 64/32 170000h to 17ffffh 0b8000h to 0bffffh sa24 0 1 1 0 0 0 x x x x 64/32 180000h to 18ffffh 0c0000h to 0c7fffh sa25 0 1 1 0 0 1 x x x x 64/32 190000h to 19ffffh 0c8000h to 0cffffh sa26 0 1 1 0 1 0 x x x x 64/32 1a0000h to 1affffh 0d0000h to 0d7fffh sa27 0 1 1 0 1 1 x x x x 64/32 1b0000h to 1bffffh 0d8000h to 0dffffh sa28 0 1 1 1 0 0 x x x x 64/32 1c0000h to 1cffffh 0e0000h to 0e7fffh sa29 0 1 1 1 0 1 x x x x 64/32 1d0000h to 1dffffh 0e8000h to 0effffh sa30 0 1 1 1 1 0 x x x x 64/32 1e0000h to 1effffh 0f0000h to 0f7fffh sa31 0 1 1 1 1 1 x x x x 64/32 1f0000h to 1fffffh 0f8000h to 0fffffh sa32 1 0 0 0 0 0 x x x x 64/32 200000h to 20ffffh 100000h to 107fffh mbm29dl34tf/bf 70 16 (continued) bank sec- tor sector address sector size ( kbytes/ kwords) ( 8) address range ( 16) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa33 1 0 0 0 0 1 x x x x 64/32 210000h to 21ffffh 108000h to 10ffffh sa34 1 0 0 0 1 0 x x x x 64/32 220000h to 22ffffh 110000h to 117fffh sa35 1 0 0 0 1 1 x x x x 64/32 230000h to 23ffffh 118000h to 11ffffh sa36 1 0 0 1 0 0 x x x x 64/32 240000h to 24ffffh 120000h to 127fffh sa37 1 0 0 1 0 1 x x x x 64/32 250000h to 25ffffh 128000h to 12ffffh sa38 1 0 0 1 1 0 x x x x 64/32 260000h to 26ffffh 130000h to 137fffh sa39 1 0 0 1 1 1 x x x x 64/32 270000h to 27ffffh 138000h to 13ffffh sa40 1 0 1 0 0 0 x x x x 64/32 280000h to 28ffffh 140000h to 147fffh sa41 1 0 1 0 0 1 x x x x 64/32 290000h to 29ffffh 148000h to 14ffffh sa42 1 0 1 0 1 0 x x x x 64/32 2a0000h to 2affffh 150000h to 157fffh sa43 1 0 1 0 1 1 x x x x 64/32 2b0000h to 2bffffh 158000h to 15ffffh sa44 1 0 1 1 0 0 x x x x 64/32 2c0000h to 2cffffh 160000h to 167fffh sa45 1 0 1 1 0 1 x x x x 64/32 2d0000h to 2dffffh 168000h to 16ffffh sa46 1 0 1 1 1 0 x x x x 64/32 2e0000h to 2effffh 170000h to 177fffh sa47 1 0 1 1 1 1 x x x x 64/32 2f0000h to 2fffffh 178000h to 17ffffh bank 1 sa48 1 1 0 0 0 0 x x x x 64/32 300000h to 30ffffh 180000h to 187fffh sa49 1 1 0 0 0 1 x x x x 64/32 310000h to 31ffffh 188000h to 18ffffh sa50 1 1 0 0 1 0 x x x x 64/32 320000h to 32ffffh 190000h to 197fffh sa51 1 1 0 0 1 1 x x x x 64/32 330000h to 33ffffh 198000h to 19ffffh sa52 1 1 0 1 0 0 x x x x 64/32 340000h to 34ffffh 1a0000h to 1a7fffh sa53 1 1 0 1 0 1 x x x x 64/32 350000h to 35ffffh 1a8000h to 1affffh sa54 1 1 0 1 1 0 x x x x 64/32 360000h to 36ffffh 1b0000h to 1b7fffh sa55 1 1 0 1 1 1 x x x x 64/32 370000h to 37ffffh 1b8000h to 1bffffh sa56 1 1 1 0 0 0 x x x x 64/32 380000h to 38ffffh 1c0000h to 1c7fffh sa57 1 1 1 0 0 1 x x x x 64/32 390000h to 39ffffh 1c8000h to 1cffffh sa58 1 1 1 0 1 0 x x x x 64/32 3a0000h to 3affffh 1d0000h to 1d7fffh sa59 1 1 1 0 1 1 x x x x 64/32 3b0000h to 3bffffh 1d8000h to 1dffffh sa60 1 1 1 1 0 0 x x x x 64/32 3c0000h to 3cffffh 1e0000h to 1e7fffh sa61 1 1 1 1 0 1 x x x x 64/32 3d0000h to 3dffffh 1e8000h to 1effffh sa62 1 1 1 1 1 0 x x x x 64/32 3e0000h to 3effffh 1f0000h to 1f7fffh sa63 1 1 1 1 1 1 0 0 0 x 8/4 3f0000h to 3f1fffh 1f8000h to 1f8fffh sa64 1 1 1 1 1 1 0 0 1 x 8/4 3f2000h to 3f3fffh 1f9000h to 1f9fffh sa65 1 1 1 1 1 1 0 1 0 x 8/4 3f4000h to 3f5fffh 1fa000h to 1fafffh sa66 1 1 1 1 1 1 0 1 1 x 8/4 3f6000h to 3f7fffh 1fb000h to 1fbfffh mbm29dl34tf/bf 70 17 (continued) note : the address range is a 20 : a- 1 if in byte mode (byte = v il ) . the address range is a 20 : a 0 if in word mode (byte = v ih ) . sector address table (mbm29dl34bf) (continued) bank sec- tor sector address sector size ( kbytes/ kwords) ( 8) address range ( 16) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa67 1 1 1 1 1 1 1 0 0 x 8/4 3f8000h to 3f9fffh 1fc000h to 1fcfffh sa68 1 1 1 1 1 1 1 0 1 x 8/4 3fa000h to 3fbfffh 1fd000h to 1fdfffh sa69 1 1 1 1 1 1 1 1 0 x 8/4 3fc000h to 3fdfffh 1fe000h to 1fefffh sa70 1 1 1 1 1 1 1 1 1 x 8/4 3fe000h to 3fffffh 1ff000h to 1fffffh bank sec- tor sector address sector size ( kbytes/ kwords) ( 8) address range ( 16) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa70 1 1 1 1 1 1 x x x x 64/32 3f0000h to 3fffffh 1f8000h to 1fffffh sa69 1 1 1 1 1 0 x x x x 64/32 3e0000h to 3effffh 1f0000h to 1f7fffh sa68 1 1 1 1 0 1 x x x x 64/32 3d0000h to 3dffffh 1e8000h to 1effffh sa67 1 1 1 1 0 0 x x x x 64/32 3c0000h to 3cffffh 1e0000h to 1e7fffh sa66 1 1 1 0 1 1 x x x x 64/32 3b0000h to 3bffffh 1d8000h to 1dffffh sa65 1 1 1 0 1 0 x x x x 64/32 3a0000h to 3affffh 1d0000h to 1d7fffh sa64 1 1 1 0 0 1 x x x x 64/32 390000h to 39ffffh 1c8000h to 1cffffh sa63 1 1 1 0 0 0 x x x x 64/32 380000h to 38ffffh 1c0000h to 1c7fffh sa62 1 1 0 1 1 1 x x x x 64/32 370000h to 37ffffh 1b8000h to 1bffffh sa61 1 1 0 1 1 0 x x x x 64/32 360000h to 36ffffh 1b0000h to 1b7fffh sa60 1 1 0 1 0 1 x x x x 64/32 350000h to 35ffffh 1a8000h to 1affffh sa59 1 1 0 1 0 0 x x x x 64/32 340000h to 34ffffh 1a0000h to 1a7fffh sa58 1 1 0 0 1 1 x x x x 64/32 330000h to 33ffffh 198000h to 19ffffh sa57 1 1 0 0 1 0 x x x x 64/32 320000h to 32ffffh 190000h to 197fffh sa56 1 1 0 0 0 1 x x x x 64/32 310000h to 31ffffh 188000h to 18ffffh sa55 1 1 0 0 0 0 x x x x 64/32 300000h to 30ffffh 180000h to 187fffh sa54 1 0 1 1 1 1 x x x x 64/32 2f0000h to 2fffffh 178000h to 17ffffh sa53 1 0 1 1 1 0 x x x x 64/32 2e0000h to 2effffh 170000h to 177fffh sa52 1 0 1 1 0 1 x x x x 64/32 2d0000h to 2dffffh 168000h to 16ffffh sa51 1 0 1 1 0 0 x x x x 64/32 2c0000h to 2cffffh 160000h to 167fffh sa50 1 0 1 0 1 1 x x x x 64/32 2b0000h to 2bffffh 158000h to 15ffffh sa49 1 0 1 0 1 0 x x x x 64/32 2a0000h to 2affffh 150000h to 157fffh mbm29dl34tf/bf 70 18 (continued) bank sec- tor sector address sector size ( kbytes/ kwords) ( 8) address range ( 16) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa48 1 0 1 0 0 1 x x x x 64/32 290000h to 29ffffh 148000h to 14ffffh sa47 1 0 1 0 0 0 x x x x 64/32 280000h to 28ffffh 140000h to 147fffh sa46 1 0 0 1 1 1 x x x x 64/32 270000h to 27ffffh 138000h to 13ffffh sa45 1 0 0 1 1 0 x x x x 64/32 260000h to 26ffffh 130000h to 137fffh sa44 1 0 0 1 0 1 x x x x 64/32 250000h to 25ffffh 128000h to 12ffffh sa43 1 0 0 1 0 0 x x x x 64/32 240000h to 24ffffh 120000h to 127fffh sa42 1 0 0 0 1 1 x x x x 64/32 230000h to 23ffffh 118000h to 11ffffh sa41 1 0 0 0 1 0 x x x x 64/32 220000h to 22ffffh 110000h to 117fffh sa40 1 0 0 0 0 1 x x x x 64/32 210000h to 21ffffh 108000h to 10ffffh sa39 1 0 0 0 0 0 x x x x 64/32 200000h to 20ffffh 100000h to 107fffh sa38 0 1 1 1 1 1 x x x x 64/32 1f0000h to 1fffffh 0f8000h to 0fffffh sa37 0 1 1 1 1 0 x x x x 64/32 1e0000h to 1effffh 0f0000h to 0f7fffh sa36 0 1 1 1 0 1 x x x x 64/32 1d0000h to 1dffffh 0e8000h to 0effffh sa35 0 1 1 1 0 0 x x x x 64/32 1c0000h to 1cffffh 0e0000h to 0e7fffh sa34 0 1 1 0 1 1 x x x x 64/32 1b0000h to 1bffffh 0d8000h to 0dffffh sa33 0 1 1 0 1 0 x x x x 64/32 1a0000h to 1affffh 0d0000h to 0d7fffh sa32 0 1 1 0 0 1 x x x x 64/32 190000h to 19ffffh 0c8000h to 0cffffh sa31 0 1 1 0 0 0 x x x x 64/32 180000h to 18ffffh 0c0000h to 0c7fffh sa30 0 1 0 1 1 1 x x x x 64/32 170000h to 17ffffh 0b8000h to 0bffffh sa29 0 1 0 1 1 0 x x x x 64/32 160000h to 16ffffh 0b0000h to 0b7fffh sa28 0 1 0 1 0 1 x x x x 64/32 150000h to 15ffffh 0a8000h to 0affffh sa27 0 1 0 1 0 0 x x x x 64/32 140000h to 14ffffh 0a0000h to 0a7fffh sa26 0 1 0 0 1 1 x x x x 64/32 130000h to 13ffffh 098000h to 09ffffh sa25 0 1 0 0 1 0 x x x x 64/32 120000h to 12ffffh 090000h to 097fffh sa24 0 1 0 0 0 1 x x x x 64/32 110000h to 11ffffh 088000h to 08ffffh sa23 0 1 0 0 0 0 x x x x 64/32 100000h to 10ffffh 080000h to 087fffh bank 1 sa22 0 0 1 1 1 1 x x x x 64/32 0f0000h to 0fffffh 078000h to 07ffffh sa21 0 0 1 1 1 0 x x x x 64/32 0e0000h to 0effffh 070000h to 077fffh sa20 0 0 1 1 0 1 x x x x 64/32 0d0000h to 0dffffh 068000h to 06ffffh sa19 0 0 1 1 0 0 x x x x 64/32 0c0000h to 0cffffh 060000h to 067fffh sa18 0 0 1 0 1 1 x x x x 64/32 0b0000h to 0bffffh 058000h to 05ffffh sa17 0 0 1 0 1 0 x x x x 64/32 0a0000h to 0affffh 050000h to 057fffh sa16 0 0 1 0 0 1 x x x x 64/32 090000h to 09ffffh 048000h to 04ffffh sa15 0 0 1 0 0 0 x x x x 64/32 080000h to 08ffffh 040000h to 047fffh mbm29dl34tf/bf 70 19 (continued) note : the address range is a 20 : a- 1 if in byte mode (byte = v il ) . the address range is a 20 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size ( kbytes/ kwords) ( 8) address range ( 16) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa14 0 0 0 1 1 1 x x x x 64/32 070000h to 07ffffh 038000h to 03ffffh sa13 0 0 0 1 1 0 x x x x 64/32 060000h to 06ffffh 030000h to 037fffh sa12 0 0 0 1 0 1 x x x x 64/32 050000h to 05ffffh 028000h to 02ffffh sa11 0 0 0 1 0 0 x x x x 64/32 040000h to 04ffffh 020000h to 027fffh sa10 0 0 0 0 1 1 x x x x 64/32 030000h to 03ffffh 018000h to 01ffffh sa9 0 0 0 0 1 0 x x x x 64/32 020000h to 02ffffh 010000h to 017fffh sa8 0 0 0 0 0 1 x x x x 64/32 010000h to 01ffffh 008000h to 00ffffh sa7 0 0 0 0 0 0 1 1 1 x 8/4 00e000h to 00ffffh 007000h to 007fffh sa6 0 0 0 0 0 0 1 1 0 x 8/4 00c000h to 00dfffh 006000h to 006fffh sa5 0 0 0 0 0 0 1 0 1 x 8/4 00a000h to 00bfffh 005000h to 005fffh sa4 0 0 0 0 0 0 1 0 0 x 8/4 008000h to 009fffh 004000h to 004fffh sa3 0 0 0 0 0 0 0 1 1 x 8/4 006000h to 007fffh 003000h to 003fffh sa2 0 0 0 0 0 0 0 1 0 x 8/4 004000h to 005fffh 002000h to 002fffh sa1 0 0 0 0 0 0 0 0 1 x 8/4 002000h to 003fffh 001000h to 001fffh sa0 0 0 0 0 0 0 0 0 0 x 8/4 000000h to 001fffh 000000h to 000fffh mbm29dl34tf/bf 70 20 sector group addresses table (mbm29dl34tf) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000xxx sa0 sga1 0000 01 x x x sa1 to sa3 10 11 sga2 0 0 0 1xxxxx sa4 to sa7 sga3 0 0 1 0xxxxxsa8 to sa11 sga4 0 0 1 1xxxxxsa12 to sa15 sga5 0 1 0 0xxxxxsa16 to sa19 sga6 0 1 0 1xxxxxsa20 to sa23 sga7 0 1 1 0xxxxxsa24 to sa27 sga8 0 1 1 1xxxxxsa28 to sa31 sga9 1 0 0 0xxxxxsa32 to sa35 sga10 1 0 0 1xxxxxsa36 to sa39 sga11 1 0 1 0xxxxxsa40 to sa43 sga12 1 0 1 1xxxxxsa44 to sa47 sga13 1 1 0 0xxxxxsa48 to sa51 sga14 1 1 0 1xxxxxsa52 to sa55 sga15 1 1 1 0xxxxxsa56 to sa59 sga16 1 1 1 1 00 x x x sa60 to sa62 01 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70 mbm29dl34tf/bf 70 21 sector group addresses table (mbm29dl34bf) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1xxxxxsa11 to sa14 sga10 0 0 1 0xxxxxsa15 to sa18 sga11 0 0 1 1xxxxxsa19 to sa22 sga12 0 1 0 0xxxxxsa23 to sa26 sga13 0 1 0 1xxxxxsa27 to sa30 sga14 0 1 1 0xxxxxsa31 to sa34 sga15 0 1 1 1xxxxxsa35 to sa38 sga16 1 0 0 0xxxxxsa39 to sa42 sga17 1 0 0 1xxxxxsa43 to sa46 sga18 1 0 1 0xxxxxsa47 to sa50 sga19 1 0 1 1xxxxxsa51 to sa54 sga20 1 1 0 0xxxxxsa55 to sa58 sga21 1 1 0 1xxxxxsa59 to sa62 sga22 1 1 1 0xxxxxsa63 to sa66 sga23 1 1 1 1 00 x x x sa67 to sa69 01 10 sga24 111111xxx sa70 mbm29dl34tf/bf 70 22 common flash memory interface code table (continued) description a 6 to a 0 dq 15 to dq 0 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 02h : amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min (write/erase) dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 1bh 0027h v cc max (write/erase) dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 1ch 0036h v pp min voltage 1dh 0000h v pp max voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min size buffer write 2 n m s 20h 0000h typical timeout per individual sector erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max timeout for byte/word write 2 n times typical 23h 0005h max timeout for buffer write 2 n times typical 24h 0000h max timeout per individual sector erase 2 n times typical 25h 0004h max timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0016h 02h : supports 8 and 16 via byte with asynchronous interface. 28h 29h 0002h 0000h max number of bytes in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0002h erase block region 1 information bit 0 to 15 : y = number of sectors bit 16 to 31 : z = size (z 256 bytes) 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information bit 0 to 15 : y = number of sectors bit 16 to 31 : z = size (z 256 bytes) 31h 32h 33h 34h 003eh 0000h 0000h 0001h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h mbm29dl34tf/bf 70 23 (continued) description a 6 to a 0 dq 15 to dq 0 minor version number, ascii 44h 0033h address sensitive unlock (dq 1 , dq 0 ) 00h = required silicon revision number (dq 7 to dq 2 ) 45h 0000h erase suspend 02h = to read & write 46h 0002h sector protection 00h = not supported x = number of sectors per group 47h 0001h sector temporary unprotection 01h = supported 48h 0001h sector protection algorithm 49h 0004h dual operation 00h = not supported x = total number of sectors in all banks except bank 1 4ah 0030h burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0000h v acc (acceleration) supply minimum 00h = not supported, dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 4dh 0085h v acc (acceleration) supply maximum 00h = not supported, dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 4eh 0095h boot type 02h = mbm29dl34bf 03h = mbm29dl34tf 4fh 00xxh program suspend 01h = supported 50h 0001h bank organization 00h = if data at 4ah is zero. x = number of banks 57h 0004h bank a region information x = number of sectors in bank a 58h 000fh bank b region information x = number of sectors in bank b 59h 0018h bank c region information x = number of sectors in bank c 5ah 0018h bank d region information x = number of sectors in bank d 5bh 0008h mbm29dl34tf/bf 70 24 n n n n functional description 1. simultaneous operation the device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . the bank can be selected by bank address (a 20 , a 19 , a 18 ) with zero latency. the device consists of the following two banks : bank 1 : 8 8 kb and 63 64 kb; bank 2 : 48 64 kb. the device can execute simultaneous operations between bank 1 and bank 2. the simultaneous operation cannot execute multi-function mode in the same bank. simultaneous operation table shows the possible combinations for simultaneous operation. (refer to 8 bank-to-bank read / write timing diagram in n timing diagram. simultaneous operation table * : by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. note: bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. the bank consists of 4 banks, bank a, bank b, bank c and bank d. bank address (ba) means to specify each of the banks. 2. standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins, and the other via the reset pin only. when using both pins, cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even when ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current consumed is less than 5 m a max. once the reset pin is set high, the device requires t rh of wake up time for output to be valid for read access. during standby mode, the output is in the high impedance state, regardless of the oe input. 3. automatic sleep mode automatic sleep mode works to restrain power consumption during read-out of device data. it can be useful in applications such as handy terminal, which requests low power consumption. to activate this mode, the devices automatically switch themselves to low power mode when the devices ad- dresses remain stable after 150 ns from data valid. it is not necessary to control ce , we , and oe in this mode. under the mode, the current consumed is typically 1 m a (cmos level) . during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are continuously read out. if the addresses are changed, the mode is automatically canceled and the devices read out the data for changed addresses. 4. autoselect the autoselect mode allows reading out of a binary code and identifies its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode mbm29dl34tf/bf 70 25 programmed with its corresponding programming algorithm. to activate this mode, the programming equipment must force v id on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses can be either high or low except a 0 , a 1 , a 2 , a 3 , and a 6 (a -1 ) . (see mbm29dl34tf/bf user bus operations tables (byte = v ih and byte = v il ) in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29dl34tf/bf command definitions table ( n device bus operation). (refer to 2. autoselect command in n command difinitions.) in word mode, a read cycle from address 00h returns the manufacturers code (fujitsu = 04h) . a read cycle at address 01h outputs device code (mbm29dl34tf=2250h, mbm29dl34bf=2253h). notice that the above applies to word mode; the addresses and codes differ from those of byte mode (refer to mbm29dl34tf/bf sector group protection verify autoselect codes tables and mbm29dl34tf/bf extended autoselect code ta b l e s i n n device bus operation.) . 5. read mode the device has two control functions required to obtain data at the outputs. ce is the power control and used for a device selection. oe is the output control and used to gate data to the output pins . address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, input hardware reset or to change ce pin from h or l 6. output disable with the oe input at a logic high level (v ih ) , output from the devices are disabled. this will cause the output pins to be in a high impedance state. 7. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the device function. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever starts later; while data is latched on the rising edge of we or ce , whichever starts first. standard microprocessor write timings are used. 8. sector group protection the devices feature hardware sector group protection. this feature will disable both program and erase opera- tions in any combination of twenty five sector groups of memory. (see sector group addresses tables (mbm29dl34tf/bf) in n sector-erase architecture) . the users side can use the sector group protection using programming equipment. the device is shipped with all sector groups that are unprotected. to activate it, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il and a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih . the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address tables (mbm29dl34tf/bf) in n sector-erase architecture define the sector address for each of the seventy one (71) individual sectors, and sector group addresses tables (mbm29dl34tf/bf) in n sector-erase architecture define the sector group address for each of the twenty five (25) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see 15. sector group protection timing diagram in n timing diagram and 5. sector group protection algorithm in n flow chart for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 mbm29dl34tf/bf 70 26 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logic 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sector. in this mode, the lower order addresses, except for a 6 , a 1 , and a 0 can be either high or low. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address will produce a logic 1 at dq 0 for a protected sector group. see mbm29dl34tf/bf sector group protection verify autoselect codes tables and mbm29dl34tf/bf extended autoselect code tables in n device bus operation for autoselect codes. 9. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ) . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to 16. temporary sector group unprotection timing diagram in n timing diagram and 6. temporary sector group unprotection algorithm in n flow chart. 10. hardware reset the devices may be reset by driving the reset pin to v il from v ih . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see 11. reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to 9. temporary sector group unpro- tection for additional functionality. 11. byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29dl34tf/bf devices. when this pin is driven high, the devices operate in the word (16-bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and the dq 8 to dq 15 bits are ignored. refer to 12. timing diagram for word mode configuration, 13. timing diagram for byte mode configuration and 14. byte timing diagram for write operations in n timing diagram for the timing diagram. 12. boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 8 k byte boot sectors independently of whether those sectors were protected or unprotected using the method described in sector group protection. the two outermost 8 k byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. (mbm29dl34tf : sa69 and sa70, mbm29dl34bf : sa0 and sa1) if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 8 k byte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two mbm29dl34tf/bf 70 27 sectors depends on whether they were last protected or unprotected using the method described in sector group protection. 13. accelerated program operation the device offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60 % . this function is primarily intended to allow high speed program- ming, so caution is needed as the sector group become temporarily unprotected. the system would use a fact program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see 18. accelerated program timing diagram in n timing diagram. erase operation at acceleration mode is strictly prohibited. mbm29dl34tf/bf 70 28 n n n n command definitions device operations are selected by writing specific address and data sequences into the command register. some commands are required bank address (ba) input. when command sequences are inputted to bank being read, the commands have priority than reading. mbm29dl34tf/bf command definitions table in n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover both reset commands are functionally equivalent, resetting the device to the read mode. please note that commands must be asserted to dq 7 to dq 0 and dq 8 to dq 15 bits are ignored. 1. reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the reset operation is initiated by writing the reset command sequence into the command register. the device remains enabled for reads until the command register contents are altered. the device will automatically be in the reset state after power-up. in this case, a command sequence is not required to read data. 2. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. therfore, manufacture and device codes must be accessible while the devices reside in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, applying high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. following the command write, in word mode, a read cycle from address (ba) 00h returns the manufacturers code (fujitsu = 04h) . a read cycle at address (ba) 01h outputs device code. notice that the above applies to word mode. the addresses and codes differ from those of byte mode. (refer to mbm29dl34tf/bf sector group protection verify autoselect codes tables and mbm29dl34tf/bf extended autoselect code tables in n device bus operation.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address (ba) 02h for 16 ( (ba) 04h for 8). scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logic 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see mbm29dl34tf/bf sector group protection verify autoselect codes tables and mbm29dl34tf/bf extended autoselect code tables in n device bus operation.) the manufacture and device codes can be allowed reading from selected bank. to read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the flash memory, the device and manu- facture codes should be read from the other bank where is not contain the software. to terminate the operation, it is necessary to write the reset command sequence into the register. to execute the autoselect command during the operation, reset command must be written before the autoselect command. 3. byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data mbm29dl34tf/bf 70 29 write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling) , dq 6 (toggle bit) , or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. hence, data polling requires the same address which is being programmed. if hardware reset occurs during the programming operation, the data being written is not guaranteed. programming is allowed in any address sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. but a read from reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. note that attempting to program a 1 over 0 will result in programming failure. this precaution is the same with fujitsu standard nor devices. 1. embedded program tm algorithm in n flow chart illustrates the embed- ded program tm algorithm using typical command strings and bus operations. 4. program suspend/resume the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during the embedded program operation immediately suspends the programming. the program suspend command can also be issued during a pro- gramming operation while an erase is suspended. the bank addresses of sector being programmed should be set when writing the program suspend command. when the program suspend command is written during a programming process, the device halts the program operation within 1 m s and updates the status bits. after the program operation has been suspended, the system can read data from any address. the data at program-suspended address is not valid. normal read timing and command definitions apply. after the program resume command (30h) is written, the device reverts to programming. the bank addresses of sectors being suspended should be set when writing the program resume command. the system can determine the status of the program operation using the dq 7 or dq 6 status bits, just as in the standard program operation. see write operation status for more information. the system also writes autoselect command sequence in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits from the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the program resume command (address bits are bank address) to exit from the program suspend mode and continue programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device resumes programming. 5. chip erase chip erase is a six bus cycle operation. it begins two unlock write cycles followed by writing the set-up command, and two unlock write cycles followed by the chip erase command which is invokes the embeded erase algorithm. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm the devices will automatically program and verify the entire memory for an all zero data pattern prior mbm29dl34tf/bf 70 30 to electrical erase (preprogram function) . the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) ,dq 2 (toggle bit ii ), or ry/by output signal. the chip erase begins on the rising edge of the last ce or we , whichever happens first from last command sequence and completes when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time = sector erase time all sectors + chip program time (preprogramming) 2. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. 6. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations. this sequence is followed by writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than erase time-out time (t tow ). otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be reoccur after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we , whichever happens first, will initiate the execution of the sector erase command (s) . if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see 16. dq 3 sector erase timer.) resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to 12. write operation status for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38) . sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase using the embedded erase algorithm. when erasing a sector or sectors, the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) , or ry/by . the sector erase begins after the t tow time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and completes when the data on dq 7 is 1 (see 12. write operation status.) at which time the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time = [sector erase time + sector program time (preprogramming) ] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. 2. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. 7. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform read or program to a sector not being erased. this command is applicable only during the sector erase operation within the time-out period for sector erase. writing the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erasing or suspending should be set when writing the erase suspend or erase resume command. mbm29dl34tf/bf 70 31 when the erase suspend command is written during the sector erase operation, the devices take maximum of t spd to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/by output pin will be at high-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see 17. dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, it is the same as programming in the regular program mode, except that the data must be programmed to sectors that are not erase-suspended. reading successively from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. 8. extended command (1) fast mode set/reset the device has fast mode function. it dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming consists of two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to 8. embedded program tm algorithm for fast mode in n flow chart.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) . (refer to 8. embedded program tm algorithm for fast mode in n flow chart.) (3) extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedures, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set v il for the other addresses pins is recommended) , and write extended sector group protection command (60h) . a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set and write a command (40h) . following the command write, a logic 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logic 0, write extended sector group protection command (60h) again. to terminate the operation, set reset pin to v ih . (refer to 17. extended sector group protection timing diagram in n timing diagram and 7. extended sector group protection algorithm in n flow chart.) mbm29dl34tf/bf 70 32 (4) query command (cfi : common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward-compatible software sup- port for the specified flash device families. refer to common flash memory interface code. the operation is initiated by writing the query command (98h) into the command register. the bank address should be set when writing this command. then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0 in word mode (16 bit) read. refer to the common flash memory interface code table. to terminate operation, it is necessary to write the reset command sequence into the register. (see common flash memory interface code table in n sector-erase architecture.) 9. hiddenrom region the hiddenrom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hiddenrom region is protected, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hiddenrom region is 256 bytes in length and is stored at the same address of the 8 kb sectors. the mbm29dl34tf occupies the address of the byte mode 3fe000h to 3fe0ffh (word mode 1ff000h to 1ff07fh) and the mbm29dl34bf type occupies the address of the byte mode 000000h to 0000ffh (word mode 000000h to 00007fh) . after the system writes the enter hiddenrom command sequence, it may read the hiddenrom region by using the addresses normally occupied by the boot sectors. that is, the device sends all commands that would normally be sent to the boot sectors to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. 10. hiddenrom entry command the device has a hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. programming is allowed in this area until it is protected. however, once it gets protected, it is impossible to unprotect. therefore, extreme caution is required. the hiddenrom area is 256 bytes. this area is normally the outermost 8 kbyte boot block area in bank 1. therefore, write the hiddenrom entry command sequence to enter the hiddenrom area. it is called hidden- rom mode when the hiddenrom area appears. sectors other than the boot block area sa0 can be read during hiddenrom mode. read/program of the hid- denrom area is possible during hiddenrom mode. write the hiddenrom reset command sequence to exit the hiddenrom mode. the bank address of the hiddenrom should be set on the third cycle of this reset command sequence. in hiddenrom mode, the simultaneous operation cannot be executed multi-function mode between the hid- denrom area and the bank 1. 11. hiddenrom program command to program the data to the hiddenrom area, write the hiddenrom program command sequence during hid- denrom mode. this command is the same as the usual program command, except that it needs to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data pooling, dq 6 toggle bit and ry/by pin. you should pay attention to the address to be programmed. if an address not in the hiddenrom area is selected, the previous data will be deleted. 12. hiddenrom protect command there are two methods to protect the hiddenrom area. one is to write the sector group protect setup command (60h) , set the sector address in the hiddenrom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the hiddenrom mode. the same command sequence may be used mbm29dl34tf/bf 70 33 because it is the same as the extension sector group protect in the past, except that it is in the hiddenrom mode and does not apply high voltage to the reset pin. please refer to 7. extended command (3) extended sector group protection for details of extension sector group protect setting. the other method is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hiddenrom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. apply write pulse again. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same as the sector group protect previously men- tioned. refer to 8. secor group protection in n functional description for details of the sector group protect setting. take note that other sector groups will be affected if an address other than those for the hiddenrom area is selected for the sector group address, so please be careful. pay close attention that once it is protected, protection cannot be cancelled. 13. write operation status detailed in hardware sequence flags table are all the status flags that can determine the status of the bank for the current mode operation. the read operation from the bank that does not operate embedded algorithm returns a data of memory cell. these bits offer a method for determining whether a embedded algorithm is completed properly. the information on dq 2 is address sensitive. if an address from an erasing sector is con- secutively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows the user to determine which sectors are erasing. the status flag is not output from bank (non-busy bank) not executing embedded algorithm. for example, there is bank (busy bank) which is now executing embedded algorithm. when the read sequence is [1] mbm29dl34tf/bf 70 34 14. dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the devices will produce reverse data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm, an attempt to read the device will produce a 1 at the dq 7 output. the flow chart for data polling (dq 7 ) is shown in 3. data polling algorithm in n flow chart. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address of the sectors being erased, not protected sector. otherwise, the status become invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags table.) see 6. data polling during embedded algorithm operation timing diagram in n timing diagram for the data polling timing specifications and diagrams. 15. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 1 m s and then stop toggling with the data unchanged. in erase, the devices will erase all the selected sectors except for the protected ones. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 m s and then drop back into read mode, having data kept remined. either ce or oe toggling will cause the dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erasing or is erase-suspended. when a bank is actively erasing (that is, the embedded erase algorithm is in progress) , dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during the erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed. see 7. toggle bit i during embedded algorithm operation timing diagram in n timing diagram for the toggle bit i timing specifications and diagrams. mbm29dl34tf/bf 70 35 16. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in mbm29dl34tf/bf user bus operations tables (byte = v ih and byte = v il ) ( n device bus operation). the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. 17. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates a valid erase command has been written, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is high (1) , the internally controlled erase cycle has begun. if dq 3 is low (0) , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags table. 18. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also toggle bit status table and 9. dq 2 vs. dq 6 in n timing diagram. furthermore dq 2 can also be used to determine which sector is being erased. at the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. 19. reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, after the initial two read cycles, if the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see 15. dq 5 ) . if it is, the system should then determine mbm29dl34tf/bf 70 36 again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to 4. toggle bit algorithm in n flow chart.) toggle bit status table *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. 20. ry/by ready/busy the devices provide a ry/by open-drain output pin to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/write or erase operation. if the devices are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to 10. ry/by timing diagram during program/erase operations and 11. reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, the pull-up resistor needs to be connected to v cc ; multiple of devices may be connected to the host system via more than one ry/by pin in parallel. 21. data protection the devices are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. 22. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min) . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min) . if embedded erase algorithm is interrupted, the intervened erasing sector (s) is(are) not valid. 23. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle * 1 erase-suspend read (erase-suspended sector) 1 1 toggle * 1 erase-suspend program dq 7 toggle 1 * 2 mbm29dl34tf/bf 70 37 24. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logic zero while oe is a logic one. 25. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. 26. sector protection device user is able to protect each sector group individually to store and protect data. protection circuit voids both program and erase commands that are addressed to protected sectors. any commands to program or erase addressed to protected sector are ignored. (see 8. sector group protection in n functional de- scription.) mbm29dl34tf/bf 70 38 n n n n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe and reset pins is - 0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is + 13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. *4 : minimum dc input voltage on wp /acc pin is - 0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is + 10.5 v which may overshoot to + 12.0 v for periods of up to 20 ns when v cc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions notes: voltage is defined on the basis of v ss = gnd = 0 v. operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , reset * 1, * 2 v in , v out - 0.5 v cc + 0.5 v power supply voltage * 1 v cc - 0.5 + 4.0 v a 9 , oe , and reset * 1, * 3 v in - 0.5 + 13.0 v wp /acc * 1, * 4 v acc - 0.5 + 10.5 v parameter symbol part no. value unit min max ambient temperatuer t a mbm29dl34tf/bf 70 - 40 + 85 c power supply voltage v cc mbm29dl34tf/bf 70 + 2.7 + 3.6 v mbm29dl34tf/bf 70 39 n n n n maximum overshoot/maximum undershoot + 0.6 v - 0.5 v 20 ns - 2.0 v 20 ns 20 ns maximum undershoot waveform v cc + 0.5 v v cc + 2.0 v + 2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 + 13.0 v v cc + 0.5 v + 14.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 2 note : this waveform is applied for a 9 , oe , and reset . mbm29dl34tf/bf 70 40 n n n n dc characteristics *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc applying. *5: embedded algorithm (program or erase) is in progress (@5 mhz) . parameter sym bol conditions value uni t min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max - 1.0 ?+ 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max - 1.0 ?+ 1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v ?? 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 5 mhz byte ? ? 16 ma word ? 18 ce = v il , oe = v ih , f = 1 mhz byte ? ? 4 ma word ? 4 v cc active current * 2 i cc2 ce = v il , oe = v ih ?? 30 ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v, we /acc = v cc 0.3 v ? 15 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v ? 15 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v ? 15 m a v cc active current * 5 (read-while-program) i cc6 ce = v il , oe = v ih byte ?? 46 ma word ?? 48 v cc active current * 5 (read-while-erase) i cc7 ce = v il , oe = v ih byte ?? 46 ma word ?? 48 v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih ?? 35 ma acc accelerated program current i acc v cc = v cc max, wp /acc = v acc max ?? 20 ma input low level v il ?- 0.5 ?+ 0.6 v input high level v ih ? 2.0 ? v cc + 0.3 v voltage for wp /acc sector protection/ unprotection and program acceleration v acc ? 8.5 ? 9.5 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id ? 11.5 12 12.5 v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min ?? 0.45 v output high voltage level v oh1 i oh = - 2.0 ma, v cc = v cc min 2.4 ?? v v oh2 i oh = - 100 m av cc - 0.4 ?? v low v cc lock-out voltage v lko ? 2.3 2.4 2.5 v mbm29dl34tf/bf 70 41 n n n n ac characteristics ? read only operations characteristics * : test conditions : output load : 1ttl gate and 100 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or v cc timing measurement reference level input : v cc / 2 output : v cc / 2 parameter symbol test setup value * unit 70 jedec standard min max read cycle time t avav t rc ? 70 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 70 ns chip enable to output delay t elqv t ce oe = v il ? 70 ns output enable to output delay t glqv t oe ?? 30 ns chip enable to output high-z t ehqz t df ?? 25 ns output enable to output high-z t ghqz t df ?? 25 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ? 0 ? ns reset pin low to read mode ? t ready ?? 20 m s ce to byte switching low or high ? t elfl , t elfh ?? 5ns c l device under test 6.2 k w 2.7 k w diode = 1n3064 or equivalent 3.3 v diode = 1n3064 or equivalent test conditions note : c l = = = = 100 pf including jig capacitance mbm29dl34tf/bf 70 42 ? write / erase / program operations (continued) parameter symbol 70 unit jedec standard min typ max write cycle time t avav t wc 70 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low during toggle bit polling ? t aso 12 ?? ns address hold time t wlax t ah 45 ?? ns address hold time from ce or oe high during toggle bit polling ? t aht 0 ?? ns data setup time t dvwh t ds 30 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns toggle and data polling 10 ?? ns ce high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? ns read recover time before write t ghel t ghel 0 ?? ns ce setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns ce hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns write pulse width t wlwh t wp 35 ?? ns ce pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 25 ?? ns ce pulse width high t ehel t cph 25 ?? ns programming operation byte t whwh1 t whwh1 ? 4 ?m s word ? 6 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 0.5 ? s v cc setup time ? t vcs 50 ?? m s rise time to v id * 2 ? t vidr 500 ?? ns rise time to v acc * 3 ? t vaccr 500 ?? ns voltage transition time * 2 ? t vlht 4 ?? m s write pulse width * 2 ? t wpp 100 ?? m s oe setup time to we active * 2 ? t oesp 4 ?? m s mbm29dl34tf/bf 70 43 (continued) *1 : does not include the preprogramming time. *2 : for sector group protection operation. *3 : this timing is limited for accelerated program operation only. parameter symbol 70 unit jedec standard min typ max ce setup time to we active * 2 ? t csp 4 ?? m s recover time from ry/by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns reset high level period before read ? t rh 200 ?? ns byte switching low to output high-z ? t flqz ?? 30 ns byte switching high to output active ? t fhqv ?? 70 ns program/erase valid to ry/by delay ? t busy ?? 90 ns delay time from embedded output enable ? t eoe ?? 70 ns erase time-out time ? t tow 50 ?? m s erase suspend transition time ? t spd ?? 20 m s mbm29dl34tf/bf 70 44 n n n n erase and programming performance notes : typical erase conditions t a = +25 c, vcc = 2.9 v typical program conditions t a = +25 c, vcc = 2.9 v, data = checker n n n n tsop (1) pin capacitance notes : test conditions t a = + 25 c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. n n n n fbga pin capacitance notes : test conditions t a = + 25 c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. parameter limits unit comments min typ max sector erase time ? 0.5 2.0 s excludes programming time prior to erasure word programming time ? 6.0 100 m s excludes system-level overhead byte programming time ? 4.0 80 m s chip programming time ?? 100 s excludes system-level overhead program/erase cycle 100,000 ?? cycle ? parameter symbol condition value unit typ max input capacitance c in v in = 0 6.0 10.0 pf output capacitance c out v out = 0 8.5 12.0 pf control pin capacitance c in2 v in = 0 8.0 11.0 pf wp /acc pin capacitance c in3 v in = 0 9.0 12.0 pf parameter symbol condition value unit typ max input capacitance c in v in = 0 6.0 10.0 pf output capacitance c out v out = 0 8.5 12.0 pf control pin capacitance c in2 v in = 0 8.0 11.0 pf wp /acc pin capacitance c in3 v in = 0 9.0 12.0 pf mbm29dl34tf/bf 70 45 n n n n timing diagram ? key to switching waveforms 1. read operation timing diagram waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l" any change permitted does not apply will be steady will change from h to l will change from l to h changing state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs output valid t rc t acc t oe t df t ce t oh t oeh mbm29dl34tf/bf 70 46 2. hardware reset/read operation timing diagram 3. alternate we controlled program operation timing diagram address ce reset outputs high-z output valid address stable t rc t acc t rh t rp t rh t ce t oh address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t oe t cs t ch t oh t df notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode) . mbm29dl34tf/bf 70 47 4. alternate ce controlled program operation timing diagram address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode) . mbm29dl34tf/bf 70 48 5. chip/sector erase operation timing diagram address data v cc ce oe we 555h 2aah 555h 555h 2aah sa * t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 10h for chip erase * : sa is the sector address for sector erase. addresses = 555h (word) , aaah (byte) for chip erase. note : these waveforms are for the 16 mode (the addresses differ from 8 mode) . mbm29dl34tf/bf 70 49 6. data polling during embedded algorithm operation timing diagram 7. toggle bit i during embedded algorithm operation timing diagram t oeh t ch t oe t ce t df t busy t eoe t whwh1 or t whwh2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data * * : dq 7 = valid data (the device has completed the embedded operation.) we ce address oe dq 6 /dq 2 ry/by data t busy t aht t aht t aso t ceph t as t oeh t oeh t ce t dh t oe t oeph * toggle data toggle data toggle data stop toggling output valid * : dq 6 stops toggling (the device has completed the embedded operation) . mbm29dl34tf/bf 70 50 8. bank-to-bank read/write timing diagram 9. dq 2 vs. dq 6 ce oe address dq t ghwl t df t oe we t wp t oeh t as ba1 read command command read read read ba2 (555h) ba2 (pa) ba2 (pa) ba1 ba1 t ce t dh t df t ds (a0h) (pd) t acc t aht t as t rc t rc t wc t rc t wc t rc t ah t ceph valid output valid input valid output valid input valid output status note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2 enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe or ce note : dq 2 is read from the erase-suspended sector. mbm29dl34tf/bf 70 51 10. ry/by timing diagram during program/erase operations 11. reset , ry/by timing diagram 12. timing diagram for word mode configuration ce ry/by we rising edge of the last write pulse t busy entire programming or erase operations t rp t rb reset t ready ry/by we t ce t fhqv data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) t elfh a -1 dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 mbm29dl34tf/bf 70 52 13. timing diagram for byte mode configuration 14. byte timing diagram for write operations t elfl t acc t flqz a -1 dq 15 data output (dq 14 to dq 0 ) data output (dq 14 to dq 0 ) ce byte dq 14 to dq 0 dq 15 /a -1 ce or we t ah t as byte input valid falling edge of the last write signal mbm29dl34tf/bf 70 53 15. sector group protection timing diagram t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 20 , a 19 , a 18 a 17 , a 16 , a 15 a 14 , a 13 , a 12 a 6 , a 3 , a 2 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data sgax 01h sgay sgax : sector group address to be protected sgay : next sector group address to be protected note : a -1 is v il on byte mode. mbm29dl34tf/bf 70 54 16. temporary sector group unprotection timing diagram reset v id v ih we ce ry/by t vlht t vlht v cc t vcs t vidr t vlht program or erase command sequence unprotection period mbm29dl34tf/bf 70 55 17. extended sector group protection timing diagram v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out sgax sgax sgay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 3 , a 2 , a 0 a 1 sgax : sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 m s (min) mbm29dl34tf/bf 70 56 18. accelerated program timing diagram wp/acc v acc v ih we ce ry/by t vlht t vlht v cc t vcs t vaccr t vlht program command sequence acceleration period mbm29dl34tf/bf 70 57 n n n n flow chart 1. embedded program tm algorithm 555h/aah 555h/a0h 2aah/55h no no yes yes start write program command sequence (see below) increment address program address/program data programming completed last address ? verify data ? embedded program algorithm in progress data polling device program command sequence (address/command) : embedded algorithms notes : the sequence is applied for 16 mode. the addresses differ from 8 mode. mbm29dl34tf/bf 70 58 2. embedded erase tm algorithm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional. embedded algorithms notes : the sequence is applied for 16 mode. the addresses differ from 8 mode. mbm29dl34tf/bf 70 59 3. data polling algorithm dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes va = valid address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . mbm29dl34tf/bf 70 60 4. toggle bit algorithm toggle bit = toggle? dq 5 = 1? read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va start no no yes yes toggle bit = toggle? program/erase operation not complete, write reset command program/erase operation complete no yes read dq 7 to dq 0 addr. = va *1, *2 *1 read dq 7 to dq 0 addr. = va *1, *2 *1 *1 : read toggle bit twice to determine whether or not it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. va = bank address being executed embedded algorithm. mbm29dl34tf/bf 70 61 5. sector group protection algorithm start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group ? increment plscnt read from sector group addr. = sga, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. a 20 , a 19 , a 18 , a 17 ,a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () () * * : a -1 is v il in byte mode. mbm29dl34tf/bf 70 62 6. temporary sector group unprotection algorithm start perform erase or program operations reset = v ih temporary sector group unprotection completed *2 reset = v id *1 *1 : all protected sectors are unprotected. *2 : all previously protected sectors are reprotected. mbm29dl34tf/bf 70 63 7. extended sector group protection algorithm start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector protection completed protect other sector group? increment plscnt read from sector group address remove v id from reset write reset command time out 250 m s reset = v id wait to 4 m s no yes setup next sector address device is operating in temporary sector group unprotection mode to protect secter group write 60h to secter address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to verify sector group protection write 40h to secter address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to setup sector group protection write xxxh/60h extended sector group protection entry? (addr. = sga, a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) mbm29dl34tf/bf 70 64 8. embedded program tm algorithm for fast mode 555h/aah 555h/20h (ba) xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode notes : the sequence is applied for 16 mode. the addresses differ from 8 mode. fast mode algorithm mbm29dl34tf/bf 70 65 n n n n ordering information part no. package access time (ns) remarks mbm29dl34tf70tn 48-pin plastic tsop (1) (fpt-48p-m19) normal bend 70 top sector MBM29DL34TF70PBT 48-pin plastic fbga (bga-48p-m12) 70 mbm29dl34bf70tn 48-pin plastic tsop (1) (fpt-48p-m19) normal bend 70 bottom sector mbm29dl34bf70pbt 48-pin plastic fbga (bga-48p-m12) 70 mbm29dl34 t f 70 tn device number/description mbm29dl34 32 mega-bit (4 m 8-bit or 2 m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase package type tn = 48-pin thin small outline package (tsop) normal bend pbt = fine pitch ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector mbm29dl34tf/bf 70 66 n n n n package dimensions (continued) 48-pin plastic tsop (1) (fpt-48p-m19) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * * mbm29dl34tf/bf 70 67 (continued) 48-pin plastic fbga (bga-48p-m12) dimensions in mm (inches) note : the values in parentheses are reference values. c 2001 fujitsu limited b48012s-c-3-3 9.000.20(.354.008) 0.380.10(.015.004) (stand off) (mounting height) 6.000.20 (.236.008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48-?0.450.10 (48-?.018.004) m ?0.08(.003) index h g fed c ba 6 5 4 3 2 1 c0.25(.010) .041 C.004 +.006 C0.10 +0.15 1.05 mbm29dl34tf/bf 70 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0311 ? fujitsu limited printed in japan |
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